The present invention relates to an image sensor, and more particularly, to a complementary metal oxide semiconductor (CMOS) image sensor and a method for manufacturing the same.
In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal. Among the image sensors, a charge-coupled device (CCD) has a structure in which each MOS capacitor is closely located and charges are stored in the MOS capacitor and transferred. Whereas, a CMOS image sensor employs CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits and adopts a switching mode that detects outputs sequentially. Here, MOS transistors are formed in the peripheral circuit as the same number of pixels in the CMOS image sensor.
In general, a unit pixel of a CMOS image sensor includes a photodiode PD and four NMOS transistors NX, RX, SX and DX. The four NMOS transistors NX, RX, SX and DX are configured with a transfer transistor TX for transferring photogenerated charges collected in the photodiode PD to a floating diffusion region FD, a reset transistor RX for setting the potential of the floating diffusion region FD at a desired level and emitting charges Cpd to reset the floating diffusion region FD, a drive transistor DX serving as a source follower buffer amplifier, and a select transistor SX for addressing a switching mode.
The transfer and reset transistor TX and RX employ a native NMOS transistor, and the drive and select transistors DX and SX employ a normal NMOS transistor. The reset transistor RX is used for correlated double sampling (CDS).
In the unit pixel of the CMOS image sensor as described above, light in the visible wavelength range is sensed by the photodiode PD using a native transistor, and thereafter the amount of the sensed photogenerated charges transferred to the floating diffusion node FD, i.e., a gate of the drive transistor DX, is outputted as an electrical signal at an output terminal VOUT.
FIG. 1 illustrates a sectional view of a typical CMOS image sensor.
Referring to FIG. 1, a pixel 12 having a photodiode is formed under a surface of a silicon substrate 11. A multi-layered insulating layer 13 is formed over the silicon substrate 11. Multi-layered metal interconnections, e.g., tri-layered metal interconnections M1, M2 and M3, are formed between the respective insulating layers of the multi-layered insulating layer 13.
In the typical CMOS image sensor of FIG. 1, the pixel 12 is formed under the front surface of the silicon substrate 11, and the metal interconnections M1, M2 and M3 do not exist over the photodiode of the pixel 12. Thus, light is transmitted through the front of a wafer, and reaches the photodiode after passing through the multi-layered insulating layer 13.
When using this CMOS image sensor of FIG. 1, there is no problem to realize an image in a VGA CMOS image sensor. However, if the number of pixels is rapidly increased more than 2 M, a pixel size should be reduced. This reduction of the pixel size leads to the decrease of the quantity of light incident on the photodiode, which makes sensitivity of the CMOS image sensor to be deteriorated.
To compensate such a limitation, there has been proposed a backside illumination architecture that illuminates light through a backside of the wafer after the backside of the wafer is thinned, as illustrated in FIG. 2.
FIG. 2 illustrates a sectional view of another typical CMOS image sensor with a backside illumination.
Referring to FIG. 2, a pixel 22 is formed under a front surface of a silicon substrate 21. Some of metal interconnections M1, M2 and M3 are disposed over a photodiode of the pixel 22, and light is transmitted through a backside of the silicon substrate 21.
The backside illumination architecture of FIG. 2 can prevent a loss of the quantity of light which may occur while the light passing through the insulating layer. In addition, as the metal interconnection can be formed over the photodiode, a pixel area can be increased to improve characteristic of the image sensor.
When fabricating the CMOS image sensor with the backside illumination, the backside of the silicon substrate 21 should be thinly processed. However, in order to process the backside of the silicon substrate 21 to a thickness ranging from approximately 10 μm to approximately 20 μm, the backside may be grinded after wafer or a glass is attached to a front of the silicon substrate 21. Moreover, after grinding the backside, the backside of the wafer should be thinned through chemical-etching process. Accordingly, an overall process is too complicated.
Furthermore, to connect a lead for package fabrication, there is required a process of forming a super contact 23 (hereinafter, referred to as super contact process) that connects the metal interconnection to the backside of the silicon substrate 21. Thus, to manufacture the CMOS image sensor with the backside illumination, multi-step processes are required, and thus the fabrication process becomes too complicated. Although the grinding and chemical-etching processes are performed, it is somewhat difficult to obtain the wafer of which the backside has a desired thickness. Thus, there is a limitation to realize a desired image according to the typical CMOS image sensor.